1. Field of the Invention
The present invention relates to a method for manufacturing active matrix liquid crystal displays (AMLCDs), and more particularly to a method for manufacturing AMLCDs which can prevent disconnection of signal lines and short circuit by improving the step coverage of the liquid crystal displays (LCDs) having a layered structure.
2. Description of the Related Art
In conventional AMLCDs, switching devices having integrated active elements such as thin film transistors (TFTs) are used to drive and control pixels in the LCDs. As shown in FIG. 1, a conventional LCD with TFT arrays has rectangular pixel electrodes 12 arrayed in rows and columns on a transparent substrate 11. Each of gate lines (address lines) 13 is formed between the rows of the pixel electrodes 12, and each of source lines (data lines) 14 is formed between the columns of the pixel electrodes 12. The TFTs 15 are electrically connected with the gate lines 13 and source lines 14, in the vicinity of an intersection between the gate lines 13 and the source lines 14.
FIG. 2A shows a plan view of a part of liquid crystal display elements of the conventional LCD, and FIG. 2B shows a sectional view taken along line 2Bxe2x80x942B in FIG. 2A.
Referring to FIGS. 2A and 2B, the conventional LCD includes a TFT array, a gate line 13 and a gate electrode 13a formed on a transparent glass substrate 11. An insulating layer 21 is formed to cover the gate electrode 13a and a gate bus line 13b formed on the transparent substrate 11. A source line 14 is formed across the gate line 13 on the insulating layer 21. Near each crossing point where the gate and source lines 13 and 14 cross each other, an intrinsic semiconductor layer 16 is formed on the gate electrode 13a branched out of the gate line 13. The insulating layer 21 is formed between the semiconductor layer 16 and the gate electrode 13a. A source electrode 14a which is branched out from the source bus line 14 is formed on a portion of the intrinsic semiconductor layer 16 over one side of the gate electrode 13a. A drain electrode 17 is formed over another side of the gate electrode 13a, opposite the source electrode 14a. In this manner, the TFTs having non-linear active elements are formed, in which the source and drain electrodes respond in accordance with the charges applied to the corresponding gate electrode.
An n+ semiconductor layer 22 is formed on the intrinsic semiconductor layer 16, and the source electrode 14a and the drain electrode 17, both made of metal, are formed thereon. The source and drain electrodes 14a and 17, respectively, are ohmic-contacted with the impure semiconductor layer 22.
In the TFT, as shown in FIG. 2B, the drain electrode 17 having an ohmic contact with the n+ semiconductor layer 22 is electrically connected with a pixel electrode 12 through a contact hole 19 formed in an insulating passivation layer 25. Basically, such a TFT includes the gate electrode 13a, the insulating layer 21, the intrinsic semiconductor layer 16, the impure semiconductor layer 22, the drain electrode 17 and the source electrode 14a. All of them are formed by repeating the steps of thin film-depositing, exposing and developing photo-resist by using masks and etching.
The aforementioned conventional AMLCD has a layered structure, in which each element thereof is formed of a thin layer. As the thin layers are piled up, overlapping portions are formed at each crossing area where the gate and source lines cross, and at areas where the drain electrodes are connected with the pixel electrodes on the TFTs arranged in rows and columns on the substrate.
Generally, a shape of one layer affects the shape of any other layer formed thereon. For example, if the shape of a first formed layer has a reversed taper and/or a shoulder, a second thin layer formed thereon will replicate the formed layer. That is, when a first metal layer has a reversed taper portion and/or a shoulder, an insulating layer formed thereon will replicate the formed layer in manufacturing an LCD. Consequently, any metal layer formed on such insulating layer has disconnected lines or short circuit problems.
These problems frequently occur when a thin film is formed with metals (e.g., Cr) which are hard to etch into a predetermined pattern, e.g., a tapering shape, or when a dry-etching method is used in the patterning process. In other words, the shape of a taper in a metal layer from which a drain electrode is formed determines the shape of an insulating passivation layer formed on the drain electrode, and affects the shape of a pixel electrode formed on the insulating passivation layer. The insulating passivation layer can have a desired shape only when the taper of the metal layer has a desired shape. Further, disconnection in the pixel electrode, resulting from a level difference (steps) within the drain electrode, can be prevented if the insulating passivation layer has a desired shape.
In the case where a metal layer for the drain electrode 17 is etched in a reverse-tapered shape (FIG. 3B), the insulating passivation layer 25 is formed with a shoulder 27 or possibly with a crack. Then the thin pixel electrode 12 is either disconnected or cannot be formed in a desired shape on the shoulder 27 or the crack. Moreover, when the insulating passivation layer 25 has cracks, etchant flows into the drain electrode 17 through the cracks and easily disconnects the drain electrode 17 during the etching step for forming the pixel electrode.
FIG. 3A shows an example of a disconnected line resulting from the above-mentioned shoulders or cracks and FIG. 3B shows a cross-sectional view taken along line 3Bxe2x80x943B of FIG. 3A.
As shown in FIGS. 3A and 3B, the drain electrode 17 has a reverse-tapered end. The insulating passivation layer 25 formed on the drain electrode 17 has a shoulder 27, and the pixel electrode 12 on the passivation layer 25 is disconnected where the step is formed in the passivation layer 25. This results in malfunctions and unreliable signal processing.
Therefore, in a layered structure, a good step-coverage is required for stable processing and for obtaining good manufacturing yield. However, it is very difficult to develop and manage a process for shaping a metal layer in a desired manner, after the metal layer is etched. It is also difficult to etch a thin layer made of a metal, such as Cr, to have a fine taper. Similarly, thin layers formed using a dry-etching method cause the layers to be disconnected or cause the layers to form cracks in other thin layers formed thereon. These and other problems arising from the conventional methods decrease yield in manufacturing semiconductor devices such as TFTs.
An object of the present invention is to provide a method for manufacturing a liquid crystal display in which a step-coverage in a thin-film layered structure is modified to prevent disconnection of signal lines.
Another object of the present invention is to provide a method of manufacturing a liquid crystal display which overcomes problems and disadvantages of related art.
In order to achieve this and other objects, a manufacturing method according to the present invention includes the steps of forming a first metal layer on a layer, coating photo-resist on the first metal layer, exposing and developing the photo-resist by using a mask with a lin-and-space pattern having a space width smaller than a resolution of an exposure system, etching the first metal layer into a desired pattern, forming an insulating layer on the patterned first metal layer, and forming a second metal layer on the insulating layer.
When the photo-resist formed on the first metal layer is exposed by using the mask with a comb-shaped line-and-space pattern, a first portion (P1) of the photo-resist corresponding to a space between the lines in the mask is exposed to less degree than a second portion (P2) of the photo-resist not covered by the mask. Similarly, a third portion (P3) of the photo-resist under the lines of the mask is lightly exposed, compared to the portion of the photo-resist without the mask. Thus degree of exposure in the photo-resist is P2 greater than P1 greater than P3. Each space width of the lines in the mask (i.e., the distance between the lines) is less than 2 xcexcm.
The first metal layer is etched by using the photo-resist as a mask. The portion of the first metal layer having no photo-resist thereon is etched more quickly than the other portion of the first metal layer having the photo-resist thereon, because it takes much more time for the etchant to penetrate through the photo-resist. Likewise, the portion of the first metal layer having a thin layer of photo-resist thereon is etched more quickly than the portion of the first metal layer having a thicker layer of photo-resist.
Accordingly, the portion of the first metal layer, which is covered with a photoresist having line-and space patterns, is etched to have a furrow and ridge shape with a gentle slope, and not a step shape with an abrupt end.
When the insulating layer is formed on the above first metal layer, it also has a gentle slope corresponding to the slope of the first metal layer. The second metal layer formed on the insulating layer follows the gentle slope of the insulating layer.
Where the above-mentioned method is applied to forming the crossing-points of gate and source lines, the first layer is a transparent glass substrate, the first metal layer is a gate line, and the second metal layer is a source line. When the above-mentioned method is applied to manufacturing a TFT, the first metal layer is selected to be source and drain electrodes, and the second metal layer is a pixel electrode or a conductive layer for connecting the drain electrode with the pixel electrode. The above-mentioned method can be applied to both forming the crossing-points and manufacturing the TFT.
A method for manufacturing an LCD according to the present invention is describe below. A first metal layer is formed on a transparent glass substrate by depositing a metal. A photo-resist is coated on the first metal layer, and the photo-resist is exposed and developed by using a mask having a desired pattern. Gate lines and gate electrodes are formed by etching the first metal layer. An insulating layer is formed on the substrate including the gate electrodes and gate lines. An i-semiconductor layer is formed on the insulating layer. An n+ semiconductor layer is formed on the i-semiconductor layer. A second metal layer is formed on the n+semiconductor. A photo-resist is coated on the second metal layer, and the photo-resist is exposed and developed by using a mask having a line-and-space pattern. The width of the space in the line-and-space pattern is smaller than an resolution of the exposure system. Source and drain electrodes are formed by etching the second metal layer. An insulating passivation layer is formed on the source and drain electrodes. A contact hole is formed in the insulating passivation layer. A conductive layer is formed on the insulating passivation layer. The conductive layer electrically connects the drain electrode to a pixel electrode.
The present invention is more fully described below with reference to preferred embodiments.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
Briefly described, the present invention is directed to a method for manufacturing a semiconductor device, including the steps of forming a first metal layer on a layer; forming a photo-resist pattern on the first metal layer using a mask, the mask having a line-and-space pattern whose space width si smaller than a resolution of an exposure system; and patterning the first metal layer using the photo-resist pattern so as to form a first metal pattern corresponding to the photo-resist pattern.
Furthermore, the present invention is directed to a method for manufacturing a liquid crystal display, including the steps of forming a first metal layer on a transparent substrate, forming a first photo-resist pattern on the first metal layer by using a first mask with a predetermined pattern, forming a gate electrode by etching the first metal layer using the first photo-resist pattern, forming a second metal layer on the gate electrode, forming a second photo-resist pattern on the second metal layer by using a second mask having a line-and-space pattern whose space width is smaller than a resolution of an exposure system, forming source and drain electrodes by etching the second metal layer using the second photo-resist pattern, and forming a transparent conductive layer for electrically connecting the drain electrode with a pixel electrode.